Techniques for fabricating and packaging multi-wavelength semiconductor laser array devices (chips) and their applications in system architectures

ABSTRACT

Phase masks which can be used to make both linear and curved gratings of single or multiple submicron pitches, with or without any abrupt quarter-wavelength shifts (or gradually varying finer phase shifts) simultaneously on the wafer/substrate. The phase masks are made using direct write electron or ion-beam lithography of two times the required submicron pitches of linear and curved gratings on commercially available π phase-shifting material on a quartz substrate and wet or dry etching of the π phase-shifting material. The phase masks can be used in connection with making multi-wavelength laser diode chips. The laser diodes have a ridge structure with metal shoulders on either side of the ridge. The laser diode chip, with different wavelength lasers, is bonded and interfaced to a novel microwave substrate that allows for high signal-to-noise ratio and low crosstalk. The substrate is packaged in a low loss rugged housing for WDM applications.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority from the following U.S.Provisional Applications, the disclosures of which are incorporated byreference in their entirety for all purposes:

[0002] Application No. 60/059,446, filed Sep. 22, 1997, of Mohammad A.Mazed, entitled “TECHNIQUES FOR FABRICATING AND PACKAGINGMULTI-WAVELENGTH SEMICONDUCTOR LASER ARRAY DEVICES (CHIPS) AND THEIRAPPLICATIONS IN SYSTEM ARCHITECTURES” (Attorney Docket No. 18579-1); and

[0003] Application No. 60/063,560, filed Oct. 28, 1997, of Mohammad A.Mazed, entitled “TECHNIQUES FOR FABRICATING AND PACKAGINGMULTI-WAVELENGTH SEMICONDUCTOR LASER ARRAY DEVICES (CHIPS) AND THEIRAPPLICATIONS IN SYSTEM ARCHITECTURES” (Attorney Docket No. 18579-1-1).

BACKGROUND OF THE INVENTION

[0004] This application relates generally to optical communications andmore specifically to techniques for manufacturing and packagingmulti-wavelength distributed feedback (DFB) semiconductor laser (laserdiode) arrays. All patent documents and other publications referred toherein are incorporated by reference in their entirety for all purposes.

[0005] Everywhere around the world, the ways people connect—throughvoice, video, and data—are radically changing through rapid advances ofcommunication (telephony and computing) technologies. These technologiesmay vary widely in applications, yet every technology shares a commonneed: an ever-increasing need for more and more speed and bandwidth from10 Mbit/sec to 100 Gbit/sec and beyond. The need for increasingbandwidth is equally compelling both in wireless and fiber-optictransmission networks.

[0006] While wireless technologies deliver freedom to communicatewithout any wire, they may be limited to only low to moderate bandwidthapplications at the present time. For high bandwidth applications(beyond 10 Gbit/s), wired fiber-optic technology appears to be the onlycost-effective solution at this time. For over a century standard coppercable has been used for telecommunication, but fiber-optic (cylindricalconduits of glass) can transmit voice, video, and data 100 times fasterthan standard copper cable. Unfortunately, only a minute fraction of thecapacity of fiber-optic technology has been realized as of today due tolimitation of optical-to-electronic and vice versa conversion methods.

[0007] With the invention of the erbium-doped optical fiber amplifier,the need for optical-to-electronic conversion in the networks isminimized. Thus by maintaining signal in the optical format andutilizing a wavelength division multiplexed/demultiplexed technology(WDM/WDDM, or sometimes simply WDM)—multiple different wavelengths(moderate bit rate on separate and distinct wavelengths) over the sameoptical-fiber, a large aggregate bit rate can be achieved.

[0008] Allowing a uniform amplification across many wavelengths, it ispossible to transmit more than 40 wavelengths (assuming a 100 GHz or 0.8nm wavelength separation with each wavelength operating at a bit rate of2.5 Gbit/s to 10 Gbit/s). WDM systems that are being manufactured todayutilize discrete wavelength-specific components(transmitters/multiplexers and filters/demultiplexers).

[0009] Current wavelength normalized and average WDM system price perwavelength is on the order of $60,000 for ultra long-distance (approx600 km) telecommunication applications and on the order of $25,000 forshort-distance (approx 60 km) telecommunications applications. As theprice of WDM components drops and the cost of deploying WDM technologybecomes economical, it becomes possible to deploy WDM technology in themetropolitan, local telephone, fiber-to-the-home, and data communicationmarkets.

[0010] Linear and curved gratings are the key elements of many advancedactive and passive opto-electronic devices, such as distributed feedback(DFB) lasers, distributed Bragg reflector (DBR) lasers, unstableresonator lasers with curved gratings, vertically focused lasers, andfilters. These advanced devices play significant roles in thefiber-optic communication systems for telephony, and computing.

[0011] There are a number of known techniques for fabricating gratingsof the type required, but they are typically characterized by a numberof disadvantages. For example, direct write electron beam lithographyhas the advantages of fine pitch control and the ability to producequarter-wavelength or finer phase shifts and arbitrary shaped gratings.However, it is characterized by high equipment expense and lowthroughput, and subjects the wafers to potential material damage due tothe impingement of the energetic electron beam. Other approaches using abinary phase mask have the advantages of high throughput, fine pitchcontrol, and the ability to produce quarter-wavelength or finer phaseshifts and arbitrary shaped gratings. However, they can be characterizedby complex fabrication procedures, and are limited to grating pitchescommensurate with the mask pitch (say 200 nm).

SUMMARY OF THE INVENTION

[0012] The present invention provides a robust process to manufacturephase masks which can be used to make both linear and curved gratings ofsingle or multiple submicron pitches (including continuously varyingpitches), with or without any abrupt quarter-wavelength shifts (orgradually varying finer phase shifts) simultaneously on thewafer/substrate. This allows practical commercial fabrication ofmulti-wavelength laser diode arrays (laser chips). The invention alsoprovides techniques for fabricating durable and reliable laser chips,efficiently packaging them and interfacing them to laser driver chips.The laser chips can be made using standard semiconductor processes,although embodiments of the invention further enhance some of suchprocesses to provide improved manufacturability and laser chipreliability.

[0013] The present invention utilizes direct write electron or ion-beamlithography of two times the required submicron pitches of linear andcurved gratings (with or without phase-shifted regions) on commerciallyavailable π phase-shifting material on a quartz substrate and wet or dryetching of the π phase-shifting material. Wet or dry etching of the πphase-shifting material produces an exact π phase shift which isnecessary to produce a zero order nulled π phase-shifted phase mask. Inan alternative embodiment, a π phase-shift mask is produced by directwriting on a quartz substrate and etching the quartz substrate to a veryprecise depth to cancel the zero order beams (transmitted anddiffracted). The invention thus relaxes critical pitch dimensions forelectron or ion-beam lithography fabrication of less than 200 nm pitchlinear and/or curved gratings.

[0014] The present invention also provides an improved ridge laserstructure having metal shoulders on either side of the laser's activeregion. The shoulders are formed over an insulating layer, but one ofthe shoulders is electrically connected by contact metal to the ridgewaveguide semiconductor material.

[0015] The present invention also provides an improved technique forcoupling the information-bearing signal to the laser chip with very highfidelity. This is achieved by designing a circuit that can carrymultiple signals at very high frequencies (say 10 GHz) withoutinterference (known as crosstalk) degradation. According to this aspectof the invention, metallized via holes connect metal structures above asubstrate to a backside ground plane below the substrate. In oneembodiment, the metal structures are ground lines interspersed withRF/DC transmission lines on the top surface of the substrate. The groundlines are perforated by the metallized vias. In another embodiment, thevias can be disposed in pairs distributed along the RF/DC transmissionline, with one via in each pair on one side of the RF/DC transmissionline and the other via in the pair on the other side. The metalstructures in this case can be individual wire arches overlying theRF/DC transmission line and extending into the vias on either side.

[0016] A further understanding of the nature and advantages of thepresent invention may be realized by reference to the remaining portionsof the specification and the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017]FIG. 1A shows a multi-wavelength distributed feedback (DFB) ridgelaser array according to a four-laser embodiment of the invention;

[0018]FIG. 1B shows an eight-laser embodiment;

[0019]FIG. 1C is a more detailed view of one of the DFB ridge lasers inthe array;

[0020]FIG. 2A shows the structure and operation of a binary intensitymask;

[0021]FIG. 2B shows the structure and operation of a π phase-shiftedphase mask;

[0022] FIGS. 3A-3G show the fabrication steps for a first method ofmaking a π phase-shifted phase mask;

[0023] FIGS. 4A-4G show the fabrication steps for a second method ofmaking a π phase-shifted phase mask;

[0024]FIG. 5A shows the use of a π phase-shifted phase mask to expose asubstrate;

[0025]FIG. 5B shows constant pitch and variable pitch linear and curvedgratings that can be made using a π phase-shifted phase mask;

[0026]FIGS. 5C and 5D show applications of curved gratings;

[0027] FIGS. 6A-6H show the fabrication steps for a method of making alaser chip;

[0028]FIGS. 7A and 7B are top and side sectional views of a laser chipmodule;

[0029]FIG. 7C shows a tapered transmission line;

[0030]FIG. 7D is a fragmentary top view showing an alternative fibertube arrangement;

[0031]FIG. 8A is a top plan view showing additional implementations ofthe laser chip module;

[0032]FIGS. 8B and 8C are detail views of implementations of isolationfor the RF/DC transmission lines;

[0033]FIG. 8D is a fragmented top plan view showing an alternativeexternal optical isolation scheme;

[0034]FIG. 9 is an exploded oblique view showing an alternativeembodiment of the laser chip module;

[0035]FIG. 10A is a circuit schematic showing a drive system for thelasers;

[0036]FIG. 10B shows an alternative scheme of electrically driving thelaser array;

[0037]FIG. 11 shows an embodiment of the multi-wavelength laser arraymodule in a metropolitan area telephone network; and

[0038]FIG. 12 shows an embodiment of the multi-wavelength laser arraymodule in a local area network.

DESCRIPTION OF SPECIFIC EMBODIMENTS

[0039] 1.0 Distributed Feedback (DFB) Laser Structural Overview

[0040]FIG. 1A is a schematic view of a multi-wavelength distributedfeedback (DFB) ridge laser diode array 10, according to an embodiment ofthe present invention. Laser array 10 is sometimes referred to as thelaser chip. Laser chip 10 includes a plurality, in the shown specificembodiment four, of ridge laser diode elements, designated 10 a, 10 b,10 c, and 10 d on a single substrate. Each ridge laser diode element,sometimes referred to simply as a laser, is configured to emit light ata different wavelength, the wavelengths being designated λ₁, λ₂, λ₃, andλ₄. The lasers have respective associated gratings 15 a-15 d, therespective pitches of which determine the lasers' respectivewavelengths. As will be described below, the technology of the inventionfacilitates etching gratings of different pitches on the same substrate.The number of lasers can be smaller or larger (say 8, as shown in FIG.1B).

[0041] Laser chip 10 is shown in a particular orientation that defineswhat are referred to as top and bottom; however, as will be describedbelow, the laser chip is preferably inverted before being mounted on asubstrate in a module so as to improve the heat transfer.

[0042] In the specific embodiment, the laser wavelengths are in theneighborhood of 1555 nm, for which many current fiber-opticcommunications modules and systems are configured. The wavelengths arespaced by approximately 3.2 nm, which corresponds to grating pitchesspaced by approximately 0.5 nm. For example, an embodiment of the laserchip with grating pitches of 238.5 nm, 239.0 nm, 239.5 nm, and 240.0 nmprovides operation at wavelengths of 1548.82 nm, 1552.02 nm, 1555.22 nm,and 1558.42 nm, respectively. It is also possible to have thewavelengths spaced by 0.8 nm or 1.6 nm.

[0043] The invention's ability to fabricate gratings of differentpitches on the same chip translates to an important advantage, namelythe ability to provide a multi-wavelength DFB laser chip. The chip canbe operated with any one wavelength selected at a given time, or withall wavelengths transmitting simultaneously, depending on theapplication. It is noted that the ability to transmit multiplewavelengths simultaneously from a single chip makes it possible toreduce the cost of WDM systems.

[0044] It is further noted that the invention's ability to fabricategratings of different pitches on the same chip also provides advantagesin connection with the fabrication of individual laser diodes. Theability to have gratings of multiple pitches on the wafer before thewafer is scribed into chips allows a single wafer to be scribed intomulti-wavelength laser array chips, or into single-laser chips,resulting in lasers with different wavelengths from the same wafer.

[0045] Undesirable optical, thermal, and electrical cross-talk among thelasers is minimized to some extent by physically separating the lasersby approximately 500 microns on the laser array chip and by formingisolation trenches 17 between adjacent lasers.

[0046]FIG. 1C is an enlarged view showing one of the lasers, say laser10 a. The laser's active region 20 is formed within a body ofsemiconductor material. The laser is referred to as a ridge laserbecause the body is formed with trenches 22 and 23 on either side of theactive region 20 to define a ridge 25 overlying grating 15 a. A pair ofmetal shoulders 27 a and 27 b are formed outboard of trenches 22 and 23.An upper layer of contact metal 30 (p+ contact) overlies the ridge whilea lower (backside) layer of contact metal 32 (n+ contact) is depositedon the bottom of the chip. Contact metal 30 is continues downwardlythrough and out of trench 22, and overlies shoulder 27 a to provide abond pad 35. The figure also shows schematically the various layers ofthe laser and its active region, the layers include an n+ substrate 42,a lower cladding layer 45, an active (quantum well) layer 47, a gratinglayer 50, an upper cladding layer 52, and a p+ contact layer 55. Gratingpatterns are etched into select regions of the grating layer, and theirrespective pitches define the individual laser wavelengths. Grating 15 ais shown as a hatched portion of grating layer 50.

[0047] Representative dimensions for a specific embodiment are providedfor the purpose of illustration only in order to provide context for thedetailed discussions below. Laser chip 10 is approximately 0.5 mm long(length of laser cavity) by 2.0 mm wide, so that the individual ridgelaser diodes are spaced by 0.5 mm (500 microns). While these aremacroscopic dimensions, the structures illustrated are microscopic. Forexample, ridge 25 is about 4 microns wide, trenches 22 and 23 are eachabout 30 microns wide, and shoulders 27 a and 27 b are each about 20microns wide. The trenches 17 are about 1.5 microns deep and theshoulders are about 2 microns thick.

[0048] While the various layers of the chip extend over substantiallythe whole area of the chip, the grating pattern is formed over only asmall area of the grating layer (say about 10 microns wide) and theactive region of each laser underlies its respective ridge. The gratinghas features about 0.05 microns in depth and is disposed about 0.4microns beneath the ridge and about 0.05 microns above the active layer.The active layer itself is about 1 micron thick.

[0049] The following sections in this specification describe variousaspects of the technology embodied in laser array 10. In particular, thefollowing description will include details of fabricating and using aphase mask, using the phase mask to make the grating, fabricating thelaser chip with the gratings of multiple pitches to supportmulti-wavelength operation, providing isolation between channels, andpackaging and incorporating the laser chip in a module.

[0050] 2.0 Phase Mask for Making Grating

[0051] 2.1 Comparison of Phase-Shift Mask and Binary Intensity Mask

[0052] A phase-shift mask, usually referred to as a phase mask, is usedin connection with defining the grating pattern in layer 50 of the laserchip. A phase mask provides the advantage that the mask can befabricated with twice the pitch of the desired grating features, therebyallowing finer gratings than would otherwise be possible. This can bestbe understood with reference to the following comparison between astandard binary intensity mask (BIM) and a phase mask. As will bedescribed below, the invention uses the property of a net π phase shift(based on scalar optics) allowing only symmetric m=+1 and m=−1 beams tointerfere where the zero-order beams cancel, giving rise to a spatialfrequency doubling.

[0053]FIG. 2A shows, in four registered segments, the structure andoperation of a binary intensity mask 60. The first segment of the figureshows mask 60, which includes a transparent substrate 62, such asquartz, on which are deposited regions of opaque material 65, such aschromium. The pattern of the opaque material defines the pattern to bereplicated in a layer on a semiconductor device. The pattern ischaracterized by a pitch, or alternatively by a spatial frequency thatis the reciprocal of the pitch.

[0054] The second segment of the figure is a plot showing the electricfield at mask 60 as a function of distance along the mask surface. Ascan be seen, the electric field along the direction of mask 60 hasalternating regions of maximum amplitude and zero amplitudecorresponding to the transparent regions and opaque regions,respectively.

[0055] The third segment is a plot of the electric field on the wafer.Due to interference and other effects, the electric field on the waferis generally sinusoidal about a positive offset, alternating betweenzero and a maximum amplitude, with a spatial frequency equal to thespatial frequency of the mask pattern.

[0056] The fourth segment is a plot of the resulting intensity on thewafer. The intensity on the wafer is given by the square of the electricfield, which can be seen to have the same spatial frequency as that ofthe pattern on mask 60.

[0057]FIG. 2B shows, in its corresponding four registered segments, thestructure and operation of a phase mask 70. Mask 70 is at leastpartially transparent over a portion of its surface, but includesalternating portions 72 and 75 representing an optical path differencethrough the mask. The pitch of these alternating portions is denoted Λ.In a particular embodiment, the phase shift is π radians. Accordingly,mask 70 is referred to as a π phase-shifted mask. Two embodiments of themask will be described below: one (denoted 70P below) in which the maskcomprises a substrate 77, and wherein regions 75 are defined by aseparate layer, of predefined thickness, of phase-shifting material; andone (denoted 70Q below) in which the material is monolithic quartz.

[0058] The second segment of the figure is a plot showing the opticalelectric field at mask 70 as a function of distance along the masksurface. As can be seen, the electric field along the direction of mask70 alternates about zero with a spatial frequency corresponding to thespatial frequency of the mask pattern (i.e., a pitch of Λ).

[0059] The third segment is a plot of the electric field on the wafer.Due to interference and other effects, the electric field on the waferis generally sinusoidal, oscillating about zero with the same spatialfrequency.

[0060] The fourth segment is a plot of the resulting intensity on thewafer. The intensity on the wafer is given by the square of the electricfield, and since the electric field oscillates about zero, the intensityis periodic at twice the spatial frequency as that of the pattern onmask 70 (i.e., a pitch of {fraction (Λ/2)}).

[0061] 2.2 Fabrication of Phase Mask Using Phase-Shifting Material

[0062] FIGS. 3A-3G show the fabrication steps for a first method ofmaking a zero-order nulled π phase-shifted phase mask, designated 70P,using phase-shifting material. Blanks of such phase-shifting materialare commercially available. A suitable material would be an embeddedi-line/365 nm 6% transmission or 9% transmission phase-shift blank,available from DuPont Photomasks Inc.

[0063]FIG. 3A is a schematic top view of phase mask 70P. The mask,designed in the specific embodiment for use with two-inch wafers, has agenerally opaque peripheral region 10 ₂ and a central region 105containing the phase mask elements for exposing the grating patterns onthe wafer. In this instance, only a quarter of the wafer would beexposed at a time; in other embodiments, the mask could be large enoughto cover the whole wafer. The regions containing the grating patterns,designated 110, are referred to as the grating stripes. They are denotedschematically as solid lines since they are only a few microns wide (10microns in a specific embodiment) but extend from one edge of centralregion 105 to the other. Also, as mentioned above, the gratings are on{fraction (1/2)}-mm centers (500 microns), which means that there wouldbe on the order of 50 grating stripes on the portion of the mask ratherthan the smaller number shown. Each stripe's grating pattern extendsperpendicular to the direction of the stripe, as shown in the magnifiedportion. For the particular embodiment, the grating patterns are inrepeating sequences of four, corresponding to the four wavelengths λ₁,λ₂, λ₃, and λ₄. The magnified portion also shows, in highly stylizedform, the fact that the grating patterns can be made to incorporate aphase-shifted region, such as a λ₄ phase-shifted region. Phase-shiftedregions are shown schematically as being spaced at 0.5 mm, whichcorresponds to the length of the laser cavity (one such phase shiftingregion is centered in the cavity, as will be described in detail below).

[0064]FIG. 3B is a sectional view of a π phase-shift blank that includesa quartz substrate 120 and an overlying layer of phase-shifting material122. This view is taken along line 3B-3B of FIG. 3A (it should beunderstood that FIG. 3A shows the finished phase mask while FIG. 3Bshows an early stage in the fabrication.

[0065]FIG. 3B shows the phase-shift blank having been coated with alayer of light sensitive material (such as photoresist) 125 and thephotoresist having been written directly using electron or ion beamlithography so as to expose regions 130 a-130 d, which will be used todefine grating stripes 110 on the finished phase mask. The portion ofFIG. 3B corresponds to a width on the phase mask that is slightly morethan that of a single four-wavelength chip on the wafer that will beexposed using the phase mask. The exposed regions (drawn cross-hatched)are greatly exaggerated since they are only about 10 microns wide at acenter separation of about {fraction (1/2)} millimeter (500 microns). Assuch, it shows four exposed regions, corresponding to the four lasersthat will constitute a four-laser chip.

[0066]FIG. 3C shows a sectional view taken along line 3C-3C in FIG. 3B.The drawing shows the exposed portions of region 130 a that will definethe actual grating. These exposed portions are designated 130 a-1, 130a-2, etc. This drawing is also not drawn to scale, since the features asseen from this angle are sub-micron (at twice the pitch of the gratingson the chip). The pitch of exposed portions is denoted Λ as in FIG. 2B,which, as discussed above, corresponds to a pitch of {fraction (Λ/2)} onthe exposed wafer.

[0067] One possible implementation of this process can use a singlelayer photoresist of 950 K molecular weight 2% to 5% PMMA (200 nm-500 nmthick) with an overcoat of 10 nm aluminum metal on the polymethyl methylacrylate (PMMA) to reduce surface electrical charging on thephase-shifting material due to the insulating nature of the πphase-shifting material (on a 90 mil thick quartz substrate).Alternatively, a tri-layer photoresist comprising a 2% PMMA 200 nm toplayer, an evaporated germanium or silicon 10 nm middle layer, and a 180°C. baked photoresist 200 nm bottom layer (180° C. baked photoresist spunon first) can be deposited on the π phase-shifting material (on a 90 milthick quartz). The concept of tri-layer photoresist was described in thearticle Howard et al., IEEE Transactions of Electron Devices ED-28 (11)1981 pp 1378-1381.

[0068] The direct writing of the pattern can be performed in multiplepasses with reduced electron or ion beam intensity. The desired patterncan be written on the photoresist by a multi-pass electron or ion beamlithography at 50 KV or 100 KV. The full exposure dose can be dividedover many passes to reduce non-uniformity and stitching errors duringthe electron or ion-beam writing.

[0069]FIGS. 3D and 3E are sectional views showing the photoresist-coatedphase-shifting material after development of the photoresist. As can beseen, the regions of photoresist exposed by the electron or ion beamhave been removed by the development step, leaving bare regions 135a-135 d of phase-shifting layer 122. These bare regions are segmented atthe phase mask pitch as shown in FIG. 3E, and the individual segmentsare denoted 135 a-1, 135 a-2, etc.

[0070] In the case of the single layer PMMA, the aluminum layer can beetched in an aluminum etching solution first, then the PMMA is developedby 1:1 volume ratio of methyl isobutyl ketone isopropanol, and finallyrinsed with isopropanol and dried in nitrogen.

[0071] In the case of the tri-layer resist process, the PMMA is firstdeveloped in 1:1 volume ratio of methyl isobutyl ketone isopropanol,rinsed with isopropanol and dried in nitrogen. The sample is then etchedin deionized water to remove native oxide on the germanium layer, thenthe germanium or silicon is dry etched by low pressure reactive (ormagnetically enhanced) ion etching in a pure CF₄ plasma. The hard baked180° C. photoresist is etched by low pressure reactive (or magneticallyenhanced) ion etching in pure O₂ plasma.

[0072]FIGS. 3F and 3G are sectional views showing the finished phasemask after etching bare regions 135 a-135 d of phase-shifting layer 122to replicate the pattern in the phase-shifting material, leaving bareregions 140 a-140 d of substrate 120. These bare regions are segmentedat the phase mask pitch as shown in FIG. 3G, and the individual segmentsof region 140 a are denoted 140 a-1, 140 a-2, etc. The etching ispreferably done by a process that etches the phase-shifting materialdown to the quartz substrate, but does not significantly etch the quartzsubstrate.

[0073] In the case of a single layer PMMA, the submicron pattern on theπ phase-shifting material can be wet etched utilizing diluted commercialchromium etchant. In the case of the tri-layer resist, the πphase-shifting material can be etched by mid pressure reactive ionetching (or magnetically enhanced) in a Cl₂ (80%) and O₂ (20%) gasmixture plasma. Final removal of the 180° C. baked photoresist can bedone by using a commercial photoresist stripper, high pressure reactiveion etching in pure O₂ gas plasma.

[0074] The phase mask is then subjected to final surface preparation anddeposition of a backside antireflection coating 142.

[0075] If desired, chromium can be deposited over the portions of thephase mask other than the grating stripes, using standard deposition andliftoff techniques. This can be easily done after etching the gratingpatterns. If done after, the etched grating stripes must be covered withphotoresist so that the deposited chromium can be lifted off the regionsof the grating stripes. Note that where chromium etchant is used to etchthe grating patterns in the phase-shifting material etching, it isgenerally not suitable to pattern the chromium by deposition andsubsequent photolithography and etching, since chromium etchant willalso etch the phase-shifting material.

[0076] 2.3 Fabrication of Phase Mask Using Direct Etching

[0077] FIGS. 4A-4G show the fabrication steps for a second method ofmaking a zero-order nulled π phase-shifted phase mask. This methoddiffers from the first method described above in that the pattern forthe grating is etched in a quartz blank rather than in phase-shiftingmaterial deposited on a quartz substrate. The quartz blank is originallychromium-plated (as are binary photomask blanks).

[0078]FIG. 4A is a schematic top view of phase mask 70Q. The mask isprimarily opaque (chromium coating) with grating stripes 145 disposed ina central region of the mask. As in the case of phase mask 70P, only aquarter of the wafer would be exposed at a time. Also, as above, thestripes are denoted schematically as solid lines, each stripe's gratingpattern extends perpendicular to the direction of the stripe, as shownin the magnified portion, and the grating patterns are in repeatingsequences of four, corresponding to the four wavelengths λ₁, λ₂, λ₃, andλ₄.

[0079]FIG. 4B is a sectional view of a portion of a chromium-platedquartz blank that includes a quartz plate 150 and an overlying layer ofchromium 152. This view is taken along line 4B-4B of FIG. 4A (it shouldbe understood that FIG. 4A shows the finished phase mask while FIG. 4Bshows an early stage in the fabrication). FIG. 4B shows the blank havingbeen coated with a layer of photoresist 153 and the photoresist havingbeen written directly using electron or ion beam lithography so as toexpose regions 155 a-155 d, which will be used to define grating stripes145 on the finished phase mask. As in the case of mask 70P, the portionof FIG. 4B corresponds to a width on the phase mask that is slightlymore than that of a single four-wavelength chip, the exposed regions(drawn cross-hatched) are greatly exaggerated, and shows four exposedregions, corresponding to the four lasers that will be on the finishedchip.

[0080] The process begins with preparation of 950 K molecular weight 5%PMMA (500 nm) on a 90 mil thick chromium-plated quartz plate (the 90 milthickness was chosen because it does not bow significantly over time andtemperature). Electron or ion-beam lithography can be utilized to directwrite edge alignment cross marks and stripe opening (10 micron wide andapproximately 10 mm long) at selected places on the chromium-coatedblank. The alignment cross marks and stripe openings can be wet etchedusing commercial chromium etchant. To obtain high contrast alignmentcross marks for electron beam lithography, Cr and Au (5 nm/100 nm) canbe evaporated on the selected areas of the alignment marks whilecarefully shadow masking the stripe opening area. The Cr and Aualignment marks can be lifted off and the chromium-coated blank rinsedwith isopropanol and plasma ashed utilizing O₂ gas to remove any surfaceresidue of photoresist.

[0081]FIG. 4C is a sectional view of the portion of the blank after thedevelopment of photoresist 157 and etching of the exposed chromium inthe regions corresponding to exposed regions 155 a-155 d in thephotoresist. The chromium portions remaining between the stripe regionswill remain on the finished phase mask.

[0082] The blank, with the chromium having been removed in the stripeareas, is then coated with photoresist and the grating patterns arewritten into the photoresist as described above in connection with thefabrication of mask 70P.

[0083] Utilizing the concept of a tri-layer photoresist as described inthe above-mentioned Howard et al. article, a tri-layer photoresistprocedure can be prepared on the 90 mil thick quartz substrate asfollows: 200 nm thinned AZ 5214E photoresist (AZ 5214E diluted inphotoresist thinner) baked at 180° C. for an hour, then 10 nm thickgermanium or silicon was deposited in a high vacuum evaporation system,followed by a spun-on 950 K molecular weight 2% PMMA (200 nm thick) andbaked again at 160° C. for half an hour. Electron or ion-beamlithography can be utilized to direct write the desired pattern at twicethe required actual pitches of the gratings.

[0084] As above, direct writing of the pattern is preferably performedin multiple passes with reduced electron or ion beam intensity.

[0085] Specifically, instead of writing the gratings with a single-passfull-electron or ion-beam exposure dose, the gratings are written inmultiple passes (at least 4) of electron or ion-beam exposure dose at1/(number of passes) of the full exposure dose to minimize field and/orsub-field stitching errors in the gratings. Doses can also be variedfrom the chromium/quartz boundary to the center of the quartz to obtaina uniform grating pattern. Exposed PMMA can be developed in 1:1 volumeratio of methyl isobutyl ketone: isopropanol developer, and finallyrinsed with isopropanol and dried in nitrogen gas.

[0086]FIGS. 4D and 4E are sectional views showing the photoresist-coatedblank after development of the photoresist. As can be seen, the regionsof photoresist exposed by the electron or ion beam is removed by thedevelopment step, leaving bare regions 157 a-157 d of quartz substrate150. These bare regions are segmented at the phase mask pitch as shownin FIG. 3E, and the individual segments are denoted 157 a-1, 157 a-2,etc.

[0087]FIGS. 4F and 4G are sectional views showing the finished phasemask after etching bare regions 157 a-157 d of quartz to replicate thepattern in the photoresist 153, leaving regions 160 a-160 d of reduceddepth substrate. These etched regions are segmented at the phase maskpitch as shown in FIG. 4G, and the individual etched segments of etchedregion 160 a are denoted 160 a-1, 160 a-2, etc. The etching ispreferably done by a process that etches the quartz substrate to a depthcorresponding to a π phase shift. Etched regions 160 a 1, etc., and thealternating unetched regions of quartz material therebetween ultimatelydefine the grating.

[0088] In the case of a germanium-based tri-layer photoresist, thequartz plate can be etched briefly in deionized water and dried innitrogen to remove native germanium oxide on the germanium. In bothgermanium-based and silicon-based tri-layer photoresists, the germaniumor silicon can be etched in a low pressure reactive ion (or magneticallyenhanced) etcher utilizing CF₄ gas plasma. The underlayer of hard bakedphotoresist can be etched sequentially in a low pressure reactive ion(or magnetically enhanced) etcher utilizing O₂ gas plasma and the quartzwas etched to the desired precise depth to obtain the desired π phaseshift in a low pressure reactive ion etcher (or magnetically enhancedreactive ion etcher) utilizing a CF₄—Ar mixture. Depth can be controlledby monitoring the etch time, profiling the etch depth in the testsignature areas and emission spectroscopy of the etch gas by-productsduring the etch. Final removal of the 180° C. baked photoresist can beaccomplished by using a commercially available photoresist stripper,high pressure reactive ion etching in pure O₂ gas plasma, andcommercially available nanostrip.

[0089] The phase mask is then subjected to final surface preparation anddeposition of a backside antireflection coating 162.

[0090] 3.0 Grating Fabrication and Possible Geometries

[0091]FIG. 5A shows phase mask 70, which may be fabricated as shownabove, used in connection with exposing a photoresist-coated (say, 40 nmthickness of photoresist) wafer 163 with a normally incident beam ofcoherent or non-coherent light, designated 165. This exposure andsubsequent processing is for the purpose of forming the grating patternin grating layer 50 (FIG. 1C) in the laser chip. The phase mask is incontact or near contact with the wafer (the case of near contact isexplicitly illustrated). Also shown are the various diffraction ordersincluding the m=0 order diffracted beam 165 a, the m=−1 order diffractedbeam 165 b, and the m=+1 order diffracted beam 165 c. Due to the π phaseshift, the m=0 order diffracted beam is canceled and the first orderbeams 165 b and 165 c interfere to form the image. As discussed above,the nature of the phase mask is that the patterns on the wafer have aspatial frequency that is twice that of the pattern on the phase mask.That is, the pitch of the grating pattern on the phase mask is twice thedesired/designed grating pitch. After exposure, the photoresist isdeveloped, and the grating pattern etched in the wafer using a standardwet or dry etching process.

[0092] Advantages of using a phase mask with normally incidentillumination, in addition to achieving finer patterns, include theability to make gratings of different pitches on the same substrate, andto make curved gratings.

[0093]FIG. 5B shows four different possible grating configurations thatcan be made using processes according to the invention. A linear grating170 is shown having segments 172 and 173 of a constant pitch Λ separatedby a {fraction (Λ/4)} phase-shifted region 175. Embodiments of the laserchip according to the invention include multiple linear gratings, eachwith a {fraction (λ/4)} phase-shifted region, with each grating having adifferent pitch to support multi-wavelength operation.

[0094] A curved grating 180 is shown having constant-pitch curvedgrating segments 182 and 183 separated by a {fraction (λ/4)}phase-shifted region 185. A linear grating 190 is shown having segments192 and 193 of a first constant pitch, designated Λ_(small), separatedby a segment 195 of a larger pitch, designated Λ_(large). A curvedgrating 200 is shown having curved grating segments 20 ₂ and 203 of afirst pitch Λ_(small), separated by a curved grating region 205 of alarger pitch Λ_(large).

[0095] FIGS. 5C and SD show representative applications of curvedgratings. As mentioned above, the laser chip illustrated in FIG. 1A usesfour straight gratings of different pitches, each with a {fraction(Λ/4)} phase-shifted region. The applications shown in FIGS. 5C and 5Dcan be used with many different kinds of lasers, and in these cases, thegratings are outside the laser cavities. FIG. 5C shows a verticallyfocusing laser diode configuration with a laser diode 210 and a curvedgrating 212 to provide focus at a spot 213. FIG. 5D shows a high-powerunstable resonator laser diode configuration with a laser diode 215(having curved mirrors 216 a and 216 b) and a pair of curved gratings217 a and 217 b.

[0096] 4.0 Laser Chip Fabrication

[0097] 4.1 Patterning and Etching Process

[0098] In current implementations, the laser chip fabrication beginswith the purchase of a commercially available laser diode wafer from asupplier such as EPI, located in Londonderry, N.H. Wafers may also beobtained from Semia, San Francisco, Calif. A commercially availablelaser diode wafer includes, for example, the following layers, startingfrom the top:

[0099] p+ doped top metal contact (InGaAs)

[0100] p doped upper cladding (InP/InGaAsP)

[0101] grating layer (InGaAsP)

[0102] multi-layer active region (alternating quantum well and barrierlayers)

[0103] n doped lower cladding (InP/InGaAsP)

[0104] n+ doped substrate (InP)

[0105] FIGS. 6A-6H show the fabrication steps for fabricating the ridgelaser arrays. The drawings are not to scale—for example, thicknesseshave been greatly exaggerated. In specific implementations, the laserchips are fabricated on 2-inch wafers. The wafers can be purchased withsome or all of the layers above the grating layer present or missing.Depending on the particular wafer, the gratings are etched in thegrating layer (the overlying layers, if originally present, having beenremoved), and the upper layers are regrown.

[0106] The grating patterns are etched using phase mask 70 and standardphotolithography. The exposure of the grating patterns using the phasemask was described above. As noted above, the exposure can be done usingcoherent or incoherent light. At this point, the gratings have beencovered over; however, their precise locations must be known in order toform the ridge laser structures over the gratings.

[0107]FIG. 6A is a schematic top view showing a laser wafer 250 at thepoint where the gratings, designated 255, have been etched, theoverlying semiconductor material 257 (for example, InGaAsP/InP/InGaAs)regrown, and the wafer subjected to edge opening photolithography andwet etching to locate the gratings. The regions containing the gratingpatterns, referred to as the grating stripes, are denoted schematicallyas solid lines since they are only a few microns wide (10 microns in aspecific embodiment) but extend across the wafer. Also, as mentionedabove, the gratings are on {fraction (1/2)}-mm centers (500 microns),which means that there would be on the order of 100 grating stripes onthe wafer rather than the smaller number shown. Each stripe's gratingpattern extends perpendicular to the direction of the stripe, as shownin the magnified portion.

[0108]FIG. 6B shows the portion of the wafer after an insulating layer,such as silicon nitride or silicon dioxide, has been deposited over thewafer and alignment marks 260 have been formed by photolithography andetching of the insulating layer. The alignment marks are shown ascrosses, and are located at various locations on the wafer. In aspecific embodiment, the alignment marks are located every 10 or 20chips. Since the active regions of the laser structures occupy a smallfraction of the 2-mm width of the chip, it is a simple matter to locatethe alignment marks over a portion of the chip that is removed from theactive regions (say, near one of the isolation trenches).

[0109]FIG. 6C is a schematic sectional view showing a portion of laserwafer 250 that corresponds to a little more than one laser chip inwidth. The wafer has not been separated into individual chips, so thestructures whose formation will now be described extend from one edge ofthe chip to the other (registered to the grating stripes). The gratingstripes are shown just underlying regrown material 257.

[0110]FIG. 6D shows the portion of the wafer after etching trenches 22and 23 (FIG. 1C) to define the ridge waveguide, and etching more deeplybetween the lasers' active regions to define isolation trenches 17 (FIG.1A). The trenches may be etched utilizing a combination of reactive ormagnetron enhanced reactive ion etching (methane and hydrogen gasmixture at room temperature or chlorine and argon gas mixture at 300°C.) and wet etching in hydrochloric acid and water in the volume ratioof 4:1.

[0111]FIG. 6E shows a more localized portion of the wafer afterdeposition of a conformal insulating layer 270, which can be of amaterial such as silicon nitride, silicon dioxide, or cyclotene, andsubsequent annealing to densify and relieve stress in the insulatingmaterial.

[0112]FIG. 6F shows the more localized portion of the wafer afterinsulating layer 270 has been patterned and etched to remove a portionof the insulating layer over ridge 25 to expose a region 275 of theunderlying semiconductor material. Two-micron wide openings, preciselyon top of the four-micron wide ridge waveguides (utilizing the alignmentmarks) can be made by reactive ion etching utilizing a CF₄ (98%) and O₂(2%) gas mixture.

[0113] Prior to topside metallization, the semiconductor surface can becleaned in low power O₂ plasma and buffered hydrofluoric acid, rinsedwith deionized water, and dried in nitrogen gas to remove any nativeoxide on the semiconductor surface.

[0114] Similarly, a low-power broad-area argon ion beam or low energylow-pressure electron cyclotron resonance (ECR) sequential hydrogen,nitrogen, and argon plasma can be utilized in vacuum in-situ for a shorttime to remove any native oxide on the semiconductor surface prior todeposition of shoulder metal and p-metal contact deposition.

[0115]FIG. 6G shows the more localized portion of the wafer aftermetallization along the outside edges of trenches 22 and 23 has beencarried out to define shoulders 27 a and 27 b (also see FIG. 1C).

[0116]FIG. 6H shows the more localized portion of the wafer aftercontact metal 30 has been deposited covering region 275 (the top of theridge), the inner surfaces of trench 22, and shoulder 27 a. Theselective metallization is carried out by photolithography and metaletching or metal liftoff according to well-known processes. It should berecognized that, at this point in the processing, contact metal 30,which extends to bonding metal 35, only contacts the semiconductormaterial atop the ridge while it is insulated from the inside surfacesof trench 22 by insulating layer 270 (FIG. 6E), while shoulders 27 a and27 b sit atop insulating layer 270. It is also possible to have contactmetal 30 extend to cover shoulder 27 b, as mentioned earlier.

[0117] Shoulders 27 a and 27 b and contact metal 30 may compriseconventional (Ti/Pt/Au) metal of respective thicknesses 20 nm, 60 nm,and 200 nm, deposited sequentially by either electron beam evaporationor sputtering. This can be utilized as shoulder or contact p-metal. Animproved sputtered p-metal contact (Ti/TiN/Pt/Au) of sequentialthicknesses 20 nm, 40 nm, 40 nm, and 200 nm, respectively, can also beutilized.

[0118] To improve the laser diode device reliability and lifetime, anovel metallization scheme can be utilized. In order to prevent gold(Au) in the contact from diffusing into the ridge, a four-layeralternating structure of TiN and Pt layer can be used between the Au andthe semiconductor. It is believed that this will significantly improvethe operating lifetime of the laser chip.

[0119] The wafer is then thinned (backside lapped and polished) to adesired dimension, 110 microns in one example. In one example, prior tobackside metallization, backside native oxide of the very fragile wafercan be removed in buffered hydrofluoric acid, very carefully rinsed withde-ionized water, and dried with N₂, and immediately loaded into anelectron-beam evaporator or sputtering system for backside n-metalcontact. A low-power broad-area argon ion beam orlow-energy/low-pressure electron cyclotron resonance (ECR) sequentialhydrogen, nitrogen, and argon plasma can be utilized in vacuum/in-situfor a very short time to remove any native oxide on the semiconductorsurface prior to deposition of n-metal contact deposition.

[0120] Backside n+ contact metal layer 32 (FIG. 1C) can consist ofNi/Ge/Au/Ni/Ag/Au of respective thicknesses 5 nm, 25 nm, 50 nm, 5 nm, 60nm, and 200 nm. This can be deposited sequentially by either electronbeam evaporation or sputtering, and is highly reliable. An apparentlyeven more reliable alternative backside metallization can besequentially sputtered Ge/Au/Ni/WSi₂/Ti/WSi₂/Au metallization ofrespective thicknesses 20 nm, 5 nm, 5 nm, 50 nm, 5 nm, 50 nm, 200 nm,and is believed to be the preferred configuration. The backside n-metalcontact was rapid thermal alloyed at 325° C. in a nitrogen gasenvironment. An additional bonding metal (Ti/Au 50 nm/200 nm) may bedeposited for better bonding.

[0121] The wafers are then scribed and cleaved into laser bars. Eachlaser bar has a length of {fraction (1/2)} mm (length of laser cavitiesin finished chip), but comprises multiple wafer chips, being as wide asthe wafer is wide at that location. In one example, the emitting facetsof the laser bars were then cleaned with a very low-power broad-areaargon ion beam or low-energy and low-pressure electron cyclotronresonance (ECR) sequential hydrogen, nitrogen, and argon plasmas for ashort time to remove any native oxide on both facets of the laser arrayswithout any crystalline damage to the facets.

[0122] At this point the front and back facets of the laser bars arecoated with anti-reflection coatings. In various examples, thesecoatings are durable and dense single-layer Gallium Gadolinium Garnet(GGG) or Sc₂O₃ (scandium oxide). In what is a presently preferredexample, a multi-layer Ta₂O₅ (tantalum oxide) and Al₂O₃ (aluminum oxide)dielectric was deposited by ion-beam assisted electron beam evaporationor sputtering at high deposition temperature for less than 0.1%anti-reflective coatings. In one example, the tantalum oxide andaluminum oxide thicknesses were 120 nm and 136 nm, respectively. Durableand dense coatings of single layer GGG or Sc₂O₃ or multi-layer Ta₂O₅ andAl₂O₃ can enhance the reliability and lifetime of the laser chip.

[0123] The laser bar is then scribed and cleaved into individual laserchips. The size of a four-laser multi-wavelength DFB ridge laser arraychip is about 2 mm×0.5 mm (4 mm×0.5 mm for an 8-laser chip), andsusceptible to damage during processing, testing, and packaging. Thistype of handling damage can cause severe yield loss during burn-in andcan cause reliability problems in the field. After significantexperimentation, it was found that this damage can be significantlyminimized by the overlayer of shoulder metal to protect the active layerfrom damage during processing, testing, and packaging.

[0124] 4.2 Process Summary

[0125] The laser chip fabrication steps, selected ones of which weredescribed in connection with FIGS. 6A-6H above, can be summarized asfollows.

[0126] 1 Design of multi-quantum well laser material;

[0127] 2 Epitaxial growth;

[0128] 3 Fabrication of multiple pitch gratings by phase mask;

[0129] 4 Regrowth over gratings;

[0130] 5 Identification of grating location (photolithography andetching);

[0131] 6 Deposition of an insulator (SiN_(x) or SiO₂);

[0132] 7 Definition of SiN_(x) or SiO₂ alignment marks (photolithographyand etching);

[0133] 8 Definition of ridge over gratings and isolation trenchutilizing SiN_(x)

[0134] or SiO₂ alignment marks (photolithography and etching);

[0135] 9 Deposition of conformal low stress dense SiN_(x) or SiO₂ orcyclotene;

[0136] `10 Contact opening of SiN_(x) or SiO₂ or cyclotene on top of theridge (photolithography and etching);

[0137] 11 Definition of shoulder metal (photolithography and etching orlift off)

[0138] 12 Definition of reliable contact metal on top of the ridge;(photolithography and etching or lift off);

[0139] 13 Au plating to improve p-metal step coverage;

[0140] 14 Lapping/thinning and polishing of the substrate;

[0141] 15 Surface preparation of the thinned substrate;

[0142] 16 Backside metallization;

[0143] 17 Metal alloying;

[0144] 18 Scribing wafer into laser bars;

[0145] 19 Facet coating of laser bars to improve performance andreliability; and

[0146] 20 Scribing laser bars into laser chips.

[0147] 4.3 Specific Laser Structures

[0148] The multi-quantum well (MQW) separate confinement heterostructure(SCH) InP/InGaAsP material structures for specific embodiments are fullyoptimized (composition and thickness) for DFB ridge laser arrayapplications. The active layer width in the ridge laser is 3 micron, asopposed to about 1 micron active laser width in buried heterostructurelasers. Small variations in the active layer in the ridge laser will notsignificantly change the wavelength accuracy for WDM applications. Inthe case of a ridge laser, the etching is stopped above the activelayer; in the case of a buried heterostructure, the active layer isetched through. Hence the ridge laser tends to provide betterreliability and higher wavelength yield. It is noted, however, thatridge lasers have a higher undesirable threshold current than buriedheterostructures. The quantum wells are at 1% compressive strain andbarriers are at 1% tensile strain. This strain compensation provideshigher reliability and improves the lifetime of the laser array device.The thickness and composition of the separate confinement layers arealso optimized for optimum grating coupling, higher bit-rate device, andoptimum far-field pattern of the laser array device for coupling to thesingle-mode optical fibers.

[0149] Specific implementations of the multi-quantum well (MQW) separateconfinement heterostructure (SCH) laser chip are set forth in Tables 1-4below. TABLE 1 First Growth Design #1 InGaAsP based strain compensatedMQW SCH structure at 1.55 μm emission wavelength Compo- Thick- sitionness Layer Material μm μm Level Type 10 InGaAs Contact 0.20 2E + 19p⁺⁺/Zn cap 9 InP 0.50 8E + 18 p+/Zn 8 InP 0.75 8E + 17 p/Zn 7 In(x) GaAs1.15 0.05 5E + 17 p/Zn (y) P 6 InP 0.25 5E + 17 p/Zn 5 In (x) GaAs 1.200.10 U/D (y) P 4 × 3** B In (x) GaAs 1.20 0.0150 U/D B (y) P 3 × 4* In(x) GaAs 1555 0.0094 U/D QW (y) P nm PL 2 In (x) GaAs 1.20 0.10 U/D (y)P 1 InP Buffer 2.00 5E + 17 n/S 0++ InP 1E + 19 n++/S Substrate

[0150] TABLE 2 First Growth Design #2 InGaAsP based strain compensatedMQW SCH structure at 1.55 μm emission wavelength Compo- Thick- sitionness Layer Material μm μm Level Type 12 InGaAs Contact 0.20 2E + 19p⁺⁺/Zn cap 11 InP 0.50 8E + 18 p+/Zn 10 InP 0.75 8E + 17 p/Zn 9 In(x)GaAs 1.15 0.05 5E + 17 p/Zn (y) P 8 InP 0.25 5E + 17 p/Zn 7 In (x) GaAs1.15 0.09 U/D (y) P 6 In (x) GaAs 1.20 0.08 U/D 5 × 3** B In (x) GaAs1.20 0.0150 U/D B (y) P 4 × 4* In (x) GaAs 1555 0.0094 U/D QW (y) P nmPL 3 In (x) GaAs 1.20 0.08 U/D (y) P 2 In (x) GaAs 1.15 0.09 (y) P 1 InPBuffer 2.00 5E + 17 n/S 0++ InP 1E + 19 n++/S Substrate

[0151] TABLE 3 (1*) Second/Regrowth Design Over 1.15Q Gratings Compo-Thick- sition ness Layer Material μm μm Level Type 10 InGaAs Contact0.20 2E + 19 p⁺⁺/Zn cap 9 InP 0.50 8E + 18 p+/Zn 8 InP 0.75 8E + 17 p/Zn7 In(x) GaAs 1.15Q 0.05 5E + 17 p/Zn (y) P 6 InP 0.25 5E + 17 p/Zn

[0152] TABLE 3 (2*) Second/Regrowth Design Over 1.15Q Gratings Compo-Thick- sition ness Layer Material μm μm Level Type 12 InGaAs Contact0.20 2E + 19 p⁺⁺/Zn cap 11 InP 0.50 8E + 18 p+/Zn 10 InP 0.75 8E + 17p/Zn 9 In(x) GaAs 1.15Q 0.05 5E + 17 p/Zn (y) P 8 InP 0.15 5E + 17 p/Zn

[0153] The main difference in the two designs set forth above lies inthe thickness of the grating layer (single layer 5 in design #1 andlayers 6 and 7 in design #2). The thinner layer of design #1 (0.10microns), as opposed to the combined thickness of design #2 (0.17microns), tends to provide greater device speed, but tends to presentmore difficulty in coupling the output light to the fiber.

[0154] 5.0 Laser Chip Module

[0155] 5.1 Module Overview

[0156]FIGS. 7A and 7B are top and side sectional views, drawn generallyto scale, showing laser chip 10 incorporated into a packaged module 300.A preferred package is a high-speed multi-optical fiber port “butterflystyle” high speed ceramic package. The particular package illustratedhas pins spaced by 50 mils. Suitable packages can be obtained from anumber of commercial vendors including Kyocera America, Inc., located inAliso Viejo, Calif.

[0157] In this embodiment, the laser driver chips (not shown) areoutside the module, and their RF modulation signals, superimposed on aDC bias by a bias tee (not shown), are communicated to the lasers viaRF/DC transmission lines 305, implemented as metal traces on a substrate307.

[0158] In one example, the modulation current is on the order of 65 mawhile the DC bias current is on the order of 25 ma. This implementationshows a simplified RF/DC shielding scheme wherein RF/DC transmissionlines 305 are bounded by ground lines 310, themselves also implementedas traces on substrate 307 with via holes through the substrate to abackside ground plane 315. The transmission lines and the ground linesmay be of constant width, or as shown in FIG. 7C, one or more may betapered in order to get optimum impedance matching and minimum returnloss.

[0159] Additional elements within the module include a pair ofthermistors 320 a and 320 b located on opposite sides of laser chip 10,a PIN photodiode 325, and a high heat removal capacity thermoelectriccooler (TEC) 330 mounted to the backside of the substrate.

[0160] The thermistors are coupled to a temperature-sensing circuit (notshown), which provides signals to a temperature-controlling circuit (notshown), which provides suitable voltages to TEC 330 to maintain adesired sensed temperature for stable operation. The PIN photodiode is aback facet monitor for providing a signal representing average opticalpower emitted through the back facet. In this embodiment, with a{fraction (λ/4)} phase-shifted region on the grating, both front andback facets are highly transparent, with the grating providing thefeedback mechanism. Therefore the optical power through the front andback facets should be the same, and the back facet measurement providesa measurement representing the optical power being emitted through thefront facet.

[0161] Substrate 307 is preferably a high efficiency heat spreader suchas AlN, which is then bonded to another high efficiency heat spreadersuch as diamond, and then onto TEC 330 for precise temperature control.

[0162] The thin film substrate incorporating the microwave transmissionlines may be the same heat spreader or a suitable separate substrate(incorporating the microwave transmission lines) bonded onto the commonheat spreader. In this approach, it is possible to place the laserdriver chips on a separate printed circuit board outside the lasermodule package.

[0163] Also shown in the figure are optical fibers 340 a-d that receivethe light output from the individual lasers in laser chip 10, and bringthe light outside the module through a pair of fiber tubes 342 a and 342b, with each tube accommodating a pair of fibers. Once outside themodule the fibers can be coupled to external optical elements, such as awavelength multiplexer.

[0164]FIG. 7C is a fragmentary top view of a module, designated 300′,showing an alternative arrangement for communicating the fibers out ofthe package. In this implementation, which represents a currentimplementation, a single tube 345, which accommodates all four fibers,is used rather than the pair of tubes 342 a and 342 b shown in FIGS. 7Aand 7B.

[0165]FIG. 8A is a top plan view showing additional implementations ofthe laser chip module and its external optical connections. This figureis drawn with the various elements exaggerated in size for clarity.Elements corresponding to elements in the implementation of FIGS. 7A and7B will be denoted by the same reference numeral. The implementationillustrated in this figure uses a more advanced isolation scheme for theRF/DC transmission lines, here denoted by reference numeral 350.

[0166] It is noted that the laser chip is mounted facedown on substrate307. The electrode structure underlying each laser site of laser chip 10includes a bonding electrodes 355 and 360. Bonding electrode 355communicates with ground plane 315 by a via (not separately shown). Thebackside of laser chip 10, is wire bonded to bonding electrode 355 toeffect backside grounding. Bonding electrode 360 includes a largeportion to which the laser chip's bonding metal 35 is bonded, and asmall portion which is wire bonded to the end of the active electrode ofRF/DC transmission line 350.

[0167] 5.2 Microwave Shielding

[0168] To modulate lasers at high bit rates, it is preferred to matchthe impedance of the lasers to the laser driver chips. The RF/DC signallines are matched to the impedance of the laser drivers and terminatedwith appropriate thin film resistors. Further, as mentioned above, it isdesired to provide a degree of electrical isolation between the variousRF/DC signal lines in order to avoid cross-talk between the differentsignal channels driving the individual lasers. In the embodimentillustrated in FIG. 7A, isolation is provided by interposing groundedlines between the RF/DC transmission lines 305. A more aggressiveisolation scheme is shown in FIG. 8A wherein metal transmission lines onsubstrate 307 have grounded, air-bridged U-shaped wires providing aseries of arches, which act, in effect, as a partial coaxial shield.

[0169]FIG. 8B is a fragmentary detail view showing a metal trace 380running along substrate 307 and having metallized via holes 382 a and382 b on respective sides. The pairs of holes are replicated along thelength of signal trace 380 to provide the shielding.

[0170]FIG. 8C illustrates a further refinement on this wherein theregion of the substrate below the metal trace has been etched to form achannel which is filled with a dielectric 385, with a dielectricmembrane 387 extending slightly outwardly of the edges ofdielectric-filled channel 385.

[0171] The microwave substrate materials are thermally conducting andlow loss for high frequency (5 GHz to 20 GHz) and high power (1 watt to10 watt) applications. The laser chip is bonded onto microwave substrateusing a low stress metallization (for example Ti/Pt/Au/Ti/Pt/TiN/Ti/AuSnof typical layer thicknesses 40/60/2000/40/100/40/3000 nm) usinggold-tin solder. Microwave simulations up to 10 GHz show that cross-talkis about −35 dB.

[0172] 5.3 External Optical Interface

[0173] In a representative optical scheme, each laser's output iscoupled to one of fibers 340 a-d. Since single-mode optical fiberpigtailing to a laser array is much more difficult than multi-modeoptical fiber pigtailing to a laser array due to optical mode mismatch,a microlens array is used to couple the lasers' outputs to the fibers.Thus, each laser's output is gathered and collimated by a collimatinglens 370, and a focusing lens 372 focuses the collimated light into thefiber. The figure further shows fibers 340 a-d fusion spliced torespective input ports of a wavelength multiplexer 375. The output portof multiplexer 375 is shown as fusion spliced to a compound isolationblock to reduce back reflection into the laser chip. The isolation blockis shown having a pair of lenses 390 and 392 on opposite sides of anoptical isolator 395. Light is focused by lens 392 into the end of asegment 397 of fiber, which is connected to a standard fiber connector390.

[0174]FIG. 8D is a fragmentary oblique view showing an alternativeexternal configuration where an in-line optical isolator 395 issubstituted for the compound isolation block shown in FIG. 8A.

[0175] 5.4 Configuration with Laser Drivers Inside Module

[0176]FIG. 9 is an exploded oblique view, also not to scale, of analternative configuration of the laser chip module, designated 300″.Elements corresponding to elements in the implementations of FIGS. 7A,7B, and 8A will be denoted by the same reference numeral. In thisimplementation, the laser driver chips, denoted 410, are located in veryclose proximity (less than 2 mm) to laser chip 10 within the module.

[0177] This configuration has the advantage that the laser module isvery compact. However, the laser driver chips may generate a lot of heatand at this close proximity (2 mm) to the laser chip, the generated heatfrom the laser drivers may influence the thermal and optical parametersof the multi-wavelength laser chip, despite the use of TEC 330 forprecise laser temperature control. To solve this problem, separatethermal paths for the laser chip and the laser drivers were utilized.Thus, laser driver chips are mounted to a separate heat spreader 420,which is mounted to substrate 307 by a set of thermal isolation elements425.

[0178] 5.5 Laser Drivers

[0179] The multi-wavelength DFB laser array has a common substrate (InP)for the lasers, so driving the individual lasers is difficult due tothis common cathode configuration. This can be solved by utilizing acommercial laser driver circuit in conjunction with an external currentmirror circuit. This external current mirror circuit acts as a currentsource, and allows the cathode of the laser diodes to be at groundpotential.

[0180]FIG. 10A shows a commonly available laser driver circuit 450 inconjunction with a bias circuit 455, connected to one of the lasers, saylaser 10 a, in the laser chip. In this implementation, bias circuit 455is a current source, where a PNP drive transistor configured as acurrent mirror acts as the current source. The current source suppliesthe maximum operating current to the laser. When the laser driver outputtransistor is on, the current to the laser is decreased by diversionthrough this transistor. This inverts the optical signal relative tothat normally obtained from the laser driver circuit. The off-statelaser current is thus the difference between the current source currentand the laser driver current. The above-mentioned approach represents acost. effective and efficient way of driving laser diodes made onn+substrates.

[0181]FIG. 10B shows an alternative approach where the bias circuit,designated 455′, includes an inductor and resistor. This approach wouldbe suitable if active components are to be avoided.

[0182] With properly chosen bias values, the existing feedback controlinputs to the laser driver circuit can be used as well. Not only thendoes this circuit provide superior drive capability, but it allows theuse of existing drivers in this application if desired.

[0183] 6.0 System Applications

[0184] The multi-wavelength laser chip of the present invention providesa number of advantages in WDM system applications. As mentioned above,discrete laser chips can have their individual wavelengths tuned as afunction of temperature. However, wavelength monitoring is expensive,and so economies are sometimes taken by monitoring a subset of thewavelengths in a WDM system. Given that the individual lasers in themulti-wavelength laser chip were fabricated under identical conditionsand operate under tightly coupled conditions, monitoring the wavelengthof only one of the multi-wavelength chip's lasers is likely to beadequate and reliable than monitoring a subset of the discrete lasers'wavelengths.

[0185]FIG. 11 shows an embodiment of the multi-wavelength laser arraymodule in a metropolitan area telephone network, while FIG. 12 shows anembodiment of the multi-wavelength laser array module in a local areanetwork. These are only representative of the possible systemdeployments of the multi-wavelength laser chip of the present invention.

[0186] 7.0 References

[0187] U.S. Patent Documents (hereby incorporated by reference): Pat.No. Year Author Assignee U.S. 4,517,280 1985 Okamoto et al. SumitomoU.S. 4,748,132 1988 Fukuzawa et al. Hitachi U.S. 4,846,552 1989Vieldkamp et al. US Air Force U.S. 5,413,884 1995 Koch et al. AT&T

[0188] Foreign Patent Documents (hereby incorporated by reference):323845410/1991 Japan

[0189] Non-Patent Publications (hereby incorporated by reference):

[0190] 1. M. Okai et al., “Novel method to fabricate corrugation for a{fraction (1/4)}-shifted distributed feedback laser using a gratingphoto mask,” Applied Physics Letter 55 (5), 31 July 1989, pp. 415-417.

[0191] 2. C. E. Zah et al., “1.5 mm compressive strained multiquantumwell 20 -wavelength distributed feedback laser arrays,” ElectronicsLetters 28, 23 April 1992, pp. 824-826.

[0192] 3. D. Tennant et al., “Characterization of near-field holographygratings mask for optoelectronics fabricated by electron beamlithography,” Journal of Vac. Technology B 10, November/December 1992,pp. 2530-2535.

[0193] 4. G. Pakulski et al., “Fused silica mask for printing uniformand phase adjusted gratings for distributed feedback lasers,” AppliedPhysics Letter 62 (3), 18 January 1993, pp. 222-224.

[0194] 5. Howard et al., IEEE Transactions of Electron Devices ED-28(11) 1981 pp. 1378-1381.

[0195] 8.0 Conclusion

[0196] In conclusion, it can be seen that the present invention provideselegant techniques for reducing the manufacturing cost ofmulti-wavelength semiconductor laser chips and modules. The inventionprovides these benefits generally within the bounds of knownsemiconductor processing technology. The use of a phase mask with normalillumination provides great flexibility in the grating configurations,while allowing extremely fine features to be produced.

[0197] While the above is a complete description of specific embodimentsof the invention, various modifications, alternative constructions, andequivalents may be used. Therefore, the above description should not betaken as limiting the scope of the invention as defined by the claims.

What is claimed is:
 1. A method of forming a phase mask for use withlight of a particular wavelength, the method comprising the steps of:providing a substrate having a layer of phase-shifting material thereon;coating the layer of phase-shifting material with a resist material;patterning the resist material using electron beam or ion beamlithography to define a mask grating pattern with submicron pitch;etching the exposed phase-shifting material to expose substratematerial; and removing the resist material to reveal regions ofphase-shifting material alternating with regions of exposed substratematerial according to the mask grating pattern.
 2. The method of claim 1wherein the layer of phase-shifting material causes light of theparticular wavelength passing through the substrate and a given regionof phase-shifting material to be 180 degrees out of phase with light ofthe particular wavelength passing through an adjacent region of exposedsubstrate.
 3. The method of claim 1 wherein the resist material is amulti-layer structure.
 4. The method of claim 1 wherein the mask gratingpattern includes a plurality of mask grating pitches.
 5. The method ofclaim 4 wherein the plurality of mask grating pitches are in separateregions of the phase mask.
 6. The method of claim 1 wherein the maskgrating pattern includes a phase shift corresponding to half the maskgrating pitch.
 7. The method of claim 1 wherein the mask grating patternincludes at least one curved grating pattern or at least one grating ofcontinuously varying pitch.
 8. The method of claim 1 wherein thepatterning step is carried out using multiple passes at a partial doseto reduce sub-field and field stitching errors.
 9. The method of claim 1wherein the etching step includes submicron anisotropic reactive ion(magnetron enhanced) etching of the exposed phase-shifting materialutilizing a gas mixture including chlorine and oxygen.
 10. The method ofclaim 9 wherein the gas mixture includes 80%-90% chlorine and 10%-20%oxygen.
 11. The method of claim 1 wherein: the resist material includesgermanium; and the patterning step includes removing native germaniumoxide with deionized water, followed by an isotropic reactive ionetching of the germanium with carbon tetrafluoride gas.
 12. The methodof claim 1 wherein: the resist material includes silicon; and thepatterning step includes an isotropic reactive ion etching of thesilicon with carbon tetrafluoride gas.
 13. The method of claim 1 whereinthe patterning step includes etching the resist material with oxygengas.
 14. The method of claim 1 wherein the submicron pitch is less than400 nm.
 15. A method of forming a phase mask for use with light of aparticular wavelength, the method comprising the steps of: providing asubstrate; coating the substrate with a resist material; patterning theresist material using electron beam. or ion beam lithography to define amask grating pattern with submicron pitch; etching the exposed substrateto a specified depth; and removing the resist material to reveal regionsof etched substrate alternating with regions of unetched substratematerial according to the mask grating pattern; wherein the specifieddepth is such that light of the particular wavelength passing through agiven region of etched substrate is 180 degrees out of phase with lightof the particular wavelength passing through an adjacent region ofunetched substrate.
 16. The method of claim 15 wherein the resistmaterial is a multi-layer structure.
 17. The method of claim 15 whereinthe mask grating pattern includes a plurality of mask grating pitches.18. The method of claim 17 wherein the plurality of mask grating pitchesare in separate regions of the phase mask.
 19. The method of claim 15wherein the mask grating pattern includes a phase shift corresponding tohalf the mask grating pitch.
 20. The method of claim 15 wherein the maskgrating pattern includes at least one curved grating pattern.
 21. Themethod of claim 15 wherein the patterning step is carried out usingmultiple passes at a partial dose to reduce sub-field and fieldstitching errors.
 22. The method of claim 15 wherein the etching stepincludes reactive ion etching with a gas mixture including carbontetrafluoride and argon.
 23. The method of claim 15 wherein the gasmixture includes 95%-98% carbon tetrafluoride and 2%-5% argon.
 24. Amethod of fabricating a desired device grating structure in asemiconductor optical device, the device grating structure havingfeatures characterized by one or more desired pitch values, the methodcomprising the steps of: providing a phase mask having a correspondingmask grating structure with features corresponding to the desired devicegrating structure but characterized by one or more pitch values, eachpitch value of the mask grating structure being twice the correspondingpitch value of the desired device grating structure; the features of themask grating structure being defined by alternating regions havingalternating first and second optical thicknesses; providing a substratehaving at least portions of the semiconductor device formed therein,said substrate being covered with a photoresist material; disposing thephase mask proximate or in contact with the substrate; illuminating thephase mask with normally incident light of a particular wavelength so asto expose the photoresist on the substrate; the particular wavelengthbeing such that light of the particular wavelength traveling through oneof the alternating regions of the phase mask and light traveling throughan adjacent one of the alternating regions of the phase mask are 180degrees out of phase; whereupon the light encountering the photoresistis characterized by an intensity distribution having pitch values thatare half the corresponding pitch values of the mask grating features,which intensity distribution corresponds to the desired device gratingstructure; developing the photoresist; and etching the substrate toimpose the desired device grating structure on the substrate.
 25. Themethod of claim 24 wherein the phase mask features are defined byalternating regions of (a) a phase-shifting material on a substratematerial, (b) the substrate material without phase-shifting material.26. The method of claim 24 wherein the phase mask features are definedby etched regions of a mask material alternating with unetched regionsof the mask material.
 27. The method of claim 24 wherein each pitchvalue of the desired device grating structure is less than 200 nm. 28.The method of claim 24 wherein the normally incident light is coherent.29. The method of claim 24 wherein the normally incident light isincoherent.
 30. A high power unstable resonator laser including a curvedgrating manufactured by method of claim 24 in combination with a laserdiode having curved facets.
 31. A vertically focused laser for launchinglight into a remote optical fiber comprising a curved grating fabricatedaccording to the method of claim 24 in combination with a laser diode.32. In a method of producing a semiconductor laser diode chip having asemiconductor substrate and a multi-layer laser structure formed on thesubstrate, the improvement comprising producing a low stress, dense, andlow hydrogen content silicon nitride layer using a plasma enhanced CVDprocess.
 33. In a method of producing a semiconductor laser diode chiphaving a semiconductor substrate and a multi-layer laser structureformed on the substrate, the improvement comprising producing a layer oforganic cyclotene as an insulating layer.
 34. A method of establishingreliable metallic content to p-doped semiconductor comprising:sequentially depositing layers of titanium, titanium nitride, platinum,and gold.
 35. A method of establishing reliable metallic content ton-doped semiconductor material comprising sequentially depositing layersof nickel, germanium, gold, nickel, silver, and gold.
 36. A method ofestablishing reliable metallic content to n-doped semiconductor materialcomprising sequentially depositing layers of germanium, gold, nickel,tungsten silicide, titanium, and gold.
 37. In the fabrication of asemiconductor laser having at least one light transmitting facet, theimprovement comprising removing native oxide on the facet using alow-power, broad-area argon ion beam or using a low-energy, low-pressureelectron cyclotron resonance to produce sequential hydrogen, nitrogen,and argon plasmas.
 38. A laser diode chip comprising: a semiconductorsubstrate; a multi-layer laser structure formed on said substrate, saidlaser structure bounded by an upper surface having a first and secondspaced trenches defining a ridge waveguide therebetween, said ridgewaveguide extending along a direction of light propagation; and firstand second metal shoulders formed on said outer surface at locationsproximate said trenches and separated from said ridge waveguide by saidtrenches, said shoulders extending above said top surface so as toprotect said ridge waveguide.
 39. The laser diode chip of claim 38wherein said laser structure includes a grating disposed below saidridge waveguide, said grating being disposed in a plane parallel to saidupper surface and having grating lines extending in a directionperpendicular to said direction of light propagation.
 40. The laserdiode chip of claim 39 wherein said laser grating structure includes aphase shift region corresponding to half the grating pitch.
 41. Thelaser diode chip of claim 39, and further comprising at an additionallaser structure formed on said substrate, said additional laserstructure including an additional ridge waveguide and an additionalgrating disposed below said additional ridge waveguide, said additionalgrating having a different pitch than said first-mentioned grating. 42.An antireflection coating for laser diode facets comprising Ta₂O₅(tantalum oxide) and Al₂O₃ (aluminum oxide).
 43. A laser chip modulecomprising: a housing having a plurality of pins for communicatingsignals from outside said housing to within said housing; dielectricsubstrate mounted in said housing, the substrate having an upper surfaceand a metallized lower surface; a laser chip mounted to said uppersurface of said substrate; first and second conductive signal lines onsaid upper surface of said substrate, said signal lines extending fromparticular first and second input pins to respective locations at ornear said laser chip; the substrate being formed with metallized viaholes electrically connected to said metallized lower surface, said viaholes forming a pattern such that each of said signal lines has aplurality of via holes on either side and at least some of said viaholes are located between said signal lines; and metal structureslocated above said substrate and electrically connected to saidmetallized lower surface by said via holes.
 44. The laser chip module ofclaim 43 wherein said transmission lines are of constant width.
 45. Thelaser chip module of claim 43 wherein said metal structures includemetallized traces on said substrate and contacting said via holes. 46.The laser chip module of claim 44 wherein said metallized traces are ofconstant width.
 47. The laser chip module of claim 44 wherein at leastone of said metallized traces is tapered.
 48. The laser chip module ofclaim 43 wherein: said pattern of via holes include pairs of via holesdistributed along each of said signal lines; and said metal structuresinclude wire arches extending from respective via holes on one side ofsaid signal lines to respective via holes on the other side of saidsignal holes.
 49. The laser chip module of claim 43 wherein the numberof laser diodes is eight or higher.
 50. A network including nodesconnected by fiber optic links, at least one link being terminated at anode with WDM equipment, the improvement wherein terminal equipmentoptically coupled to said WDM equipment comprises: a multi-wavelengthlaser module having a multi-wavelength ridge laser diode array chip forproviding independently modulated light at a plurality of wavelengths.